This invention relates in general to a method and apparatus for providing an asochronous centralized multi-channel DMA controller, and more particularly to a method and apparatus for providing a multi-channel DMA controller that provides low data latency, minimal data buffering, guaranteed data bandwidth, and asynchronous demand support within a bus bridging device within an AHB or ASB to APB bus system as defined by the AMBA bus definition.
The Advanced Microcontroller Bus Architecture (AMBA) specification defines an on-chip communications standard for designing high-performance embedded microcontrollers. Three distinct buses are defined within the AMBA specification: an Advanced High-performance Bus (AHB), an Advanced System Bus (ASB), and an Advanced Peripheral Bus (APB). A typical implementation of an AMBA system is shown in FIG. 1.
The AMBA AHB is for high-performance, high clock frequency system modules. The AHB acts as the high-performance system backbone bus. AHB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macrocell functions. AHB is also specified to ensure ease of use in an efficient design flow using synthesis and automated test techniques.
The AMBA ASB is for high-performance system modules. AMBA ASB is an alternative system bus suitable for use where the high-performance features of AHB are not required. ASB also supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macrocell functions.
The AMBA APB is for low-power peripherals. AMBA APB is optimized for minimal power consumption and reduced interface complexity to support peripheral functions. APB can be used in conjunction with either version of the system bus.
An AMBA-based microcontroller typically consists of a high-performance system backbone bus (AMBA AHB or AMBA ASB), able to sustain the external memory bandwidth, on which the CPU, on-chip memory and other Direct Memory Access (DMA) devices reside. This bus provides a high-bandwidth interface between the elements that are involved in the majority of transfers. Also located on the high-performance bus is a bridge to the lower bandwidth APB, where most of the peripheral devices in the system are located.
The APB provides the basic peripheral macrocell communications infrastructure as a secondary bus from the higher bandwidth pipelined main system bus. Such peripherals typically have interfaces that are memory-mapped registers, have no high-bandwidth interfaces, and are accessed under programmed control. The external memory interface is application-specific and may only have a narrow data path, but may also support a test access mode which allows the internal AMBA AHB, ASB and APB modules to be tested in isolation with system-independent test sets.
AHB is a later generation of AMBA bus that is intended to address the requirements of high-performance synthesizable designs. It is a high-performance system bus that supports multiple bus masters and provides high-bandwidth operation. The AHB implements the features required for high-performance, high clock frequency systems including burst transfers, split transactions, single-cycle bus master handover, single-clock edge operation, non-tristate implementation, and wider data bus configurations (64/128 bits). Bridging between this higher level of bus and the current ASB/APB can be done efficiently to ensure that any existing designs can be easily integrated.
An AHB design may contain one or more bus masters, typically a system would contain at least the processor and test interface. However, it would also be common for a Direct Memory Access (DMA) or Digital Signal Processor (DSP) to be included as bus masters. The external memory interface, APB bridge and any internal memory are the most common AHB slaves. Any other peripheral in the system could also be included as an AHB slave. However, low-bandwidth peripherals typically reside on the APB.
A typical AHB system design contains the following components: an AHB master, an AHB slave, an AHB arbiter, and an AHB decoder. A bus master is able to initiate read and write operations by providing an address and control information. Only one bus master is allowed to actively use the bus at any one time. A bus slave responds to a read or write operation within a given address-space range. The bus slave signals back to the active master the success, failure or waiting of the data transfer. The bus arbiter ensures that only one bus master at a time is allowed to initiate data transfers. Even though the arbitration protocol is fixed, any arbitration algorithm, such as highest priority or fair access can be implemented depending on the application requirements. An AHB would include only one arbiter, although this would be trivial in single bus master systems. The AHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer. A single centralized decoder is required in all AHB implementations.
In one particular application that utilizes the AMBA bus architecture, an implementation of a Cable Modem design, an embedded processor with memory and several peripheral functions with physical interfaces to external media sources has been implemented using the AMBA bus architecture. These external data links, such as Ethernet, USB, and Cable need access to the memory with bandwidths of xe2x88x92100 Mb/s for Ethernet transmit and Ethernet receive, 12 Mb/s for USB receive or transmit, and 40-50 Mb/s for Cable receive and 10 Mb/s for Cable transmit. These data sources must have guaranteed access to the memory for buffering prior to processing otherwise data will be lost. In addition to these external sources of data, internal functions such as memory to memory move, and DES (Decryption and Encryption Subsystem) engine processing need direct access to memory in order to off-load the processor of these tasks. A method is needed such that each peripheral had direct memory access in such a way that data bandwidth would be sufficient and data would not be lost. Of course minimizing the system design complexity and cost was a factor that affected the solution as well.
In prior attempts to address this problem, each peripheral, which may be a physical interface with data source/sink, may have been connected to a standard PCI bus. Each peripheral would need to have a DMA controller that would master the bus to write/read data to/from target memory The more the data peripherals the more complex it becomes to efficiently manage the bandwidth allocation from each asynchronous bus requestor. Essentially the system arbiter would have to prioritize requests and decide who gets the bus first. The latency each peripheral sees would be subject to how efficiently each higher priority peripheral used the bus and the bandwidth of that peripheral. The higher the latency, the more local buffering each peripheral would need in order to avoid overflow or underflow of data.
Other prior solutions to the asynchronous demand mode, which creates havoc in arbitrated systems, include a 1394 bus, which allocates isochronous channels. Each data peripheral would be guaranteed bandwidth by assigning a time slot allocated for the data. The problem in a time slice system, such as a 1394 bus, would be that the resolution of the time slots would again force a high amount of local buffering because each peripheral would not be able to make asynchronous requests which would allow them to off-load the data before it accumulates. The other problem with this system design solution is that it does not mix well with variable-rate data channels. The 1394 bus does support asynchronous channels as well as isochronous channels, but again the system complexity is higher, especially when the bandwidths of all data channels need adjustment dynamically.
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a method and apparatus for providing a multi-channel DMA controller that provides low data latency, minimal data buffering, guaranteed data bandwidth, and asynchronous demand support within a bus bridging device within an AHB to APB bus system as defined by the AMBA bus definition. The present invention solves the above described problems by providing an electronic bridging device for transferring electronic data between a first device attached to a system bus and a peripheral device attached to a peripheral bus using a bridging circuit. The DMA controller comprises a system bus interface circuit for connecting the DMA controller to the system bus, a peripheral bus interface circuit for connecting the DMA controller to the peripheral bus, a data transfer request circuit for receiving data transfer requests from devices attached to the peripheral bus, and a control logic circuit for controlling the operation of DMA data transfer operations. Immediately upon receipt of one or more data transfer requests, the bridging device performs the following operations: requests access to the system bus, concatenates all pending peripheral bus data words into a single transfer sequence, and transfers all pending requests across the bridging circuit.
Another aspect of the present invention is a method of transferring electronic data between a first device attached to a system bus and a peripheral device attached to a peripheral bus using a bridging circuit having a DMA controller. The method comprises receiving one or more data transfer requests from devices attached to the system bus and the peripheral bus, immediately requesting access to the system bus upon receipt of the data transfer requests by the DMA controller, concatenating all pending peripheral bus data words into a single transfer sequence, and transferring all pending requests across the bridging circuit.
These and various other advantages and features of novelty, which characterize the invention, are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to accompanying descriptive matter, in which there are illustrated and described specific examples of an apparatus in accordance with the invention.